David Page

FPGA Designer

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About me

Dynamic, motivated, versatile and resourceful FPGA Designer with a Bachelor's degree in Electrical Engineering and a minor in Computer Science, adept at continual learning and skill development. Extensive experience spanning over 12 years in FPGA design including video processing, high-speed interfaces, algorithm research and translation from software to hardware. Proven ability to develop, debug, and simulate complex FPGA designs. Proficient in programming languages including Bash, Python, C/C++, VHDL, and SystemVerilog.

Through my career I learned to be adaptive to new technologies by reading and understanding what I do. I know the tradeoffs that hardware design requires. I am passionate about what I’m doing, I have expertise in multiple aspects of FPGA design such as High Speed communication protocols, SystemVerilog, Verification, and algorithm development on FPGA.

I embrace a philosophy of continual learning, reading and understanding new software, method or technology is part of who I am.

I have strong interest about Web3, Blockchain, Zero-Knowledge Proof, Algorithm development on hardware, Hardware Security, Low Latency coding, Cryptography and Autonomous Driving.

FPGA Workflow

Cumulating now more than 12 years as an FPGA Designer, I have gained experience in many aspects of the flow:

  • Resource allocation
  • Constraint file declaration
  • Floorplanning for new FPGA or new modules
  • Pin assignment and pin swapping possibilities to help routing
  • VHDL coding
  • Simulation
  • SystemVerilog Verification
  • Post-placement simulation
  • Synthesis using Xilinx/Altera/Synopsys Synplify
  • and, of course, static timing analysis

Hardware design is a game of tradeoffs, I always get a pragmatic approach: by weighting the importance of each coding aspect (code complexity, latency, routing, timing...), I adapt my coding style to optimize what needs to be prioritized.


I am big on simulation. I developped for an employer a complete SystemVerilog Verification environment using an easy C++ Front-End approach and a SystemVerilog Back-End based on the book "SystemVerilog for Verification" respecting the UVM method with concepts such as interface, driver, generator, monitor. Everything was coded in order to run automated test every night. Since a major requirement for this environment was to be able to validate a computer vision algorithm, I had to find a way to generate "random" input stimulus as an image. I decided to use MATLAB and code a script that generates a valid image randomly with a seed to be able to reproduce the image. Then, I created an automation using Jenkins to run every night in order:

  1. Matlab script that generates an input image
  2. Model of the algorithm using the generated image as inpout
  3. VHDL Simulation using the SystemVerilog testbench using the same input image
  4. Comparing of the result using simple text files from both simulation

The use of this verification environment resulted in multiple corner case problems found, that were never discovered before that I could fix with the help of the model and the simulation.

DSP/Algorithm on hardware/Fixed point calculation/Floating point calculation

For the last 5 years, I've been working to maintain and optimize a computer vision algorithm. I did research on different ideas on how to improve the algorihtm, keeping a research document always up to date with the hypothesis to validate, the methodology, the results and conclusion.

I improved the algorithm in many ways, making it more precise and less error prone. I have gained a lot of experience and knowledge on how to convert a Software algorithm to VHDL, maintaining the exact same result as the model for validation.

I have played with many different DSPs configurations, maintaining and optimizing pipeline, doing mathematical operation on fixed point numbers, taking care of preventing overflows and making sure to choose an optimal range for the operation.

I also had to recode a major part of the algorithm to work with a new FPGA and change the fixed point calculation to floating point operation which was a new capabilities of the DSPs of this new FPGA.

High Speed Interfaces/DisplayPort/Interlaken

I have experience in High Speed communication protocols by implementing support for DisplayPort and an optical fiber communication between multiple devices. I implemented a third party DisplayPort IP from scratch: Implement on a demo board before integrating on our own design. I had to:

  • Select the optimal clocking ressources
  • Configure the clocking
  • Integrate the IP
  • Simulate the IP
  • Interface with the rest of our logic

For the optical fiber communication I decided to use the Interlaken Protocol using Altera Transceiver IP. I followed the same steps of Configuration, Integration, Simulation and Interface.

I also faced a problem with the routing of the board: High Speed component were placed in a way that created illegal routing inside the FPGA. By carefully reading the specification I was able to use the same clock source for multiple High Speed devices: I prevented the need to redesign the routing of the board and decreased the number of resource used in the FPGA


For many years my principal operating system has been Linux, I am as familiar and at ease with Linux or Windows. I create a bunch of bash script and tcl script regularly to automatise stuff. I created a whole project in Python for an employer and I am very proefficient in this language.